The 2021 International Solid-State Circuits Conference was held online from Feb.13th-22th. Ruiqi Guo, the Ph.D. student from Thinker-Lab, gave an oral presentation titled “A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization”. A 3.31×2.71mm2 computing-in-memory processor in 28nm technology achieved 5.99-to-691.1TOPS/W energy efficiency. Ruiqi Guo is the first author of this paper, professor Shouyi Yin is the corresponding author. This paper is also co-authored by Prof. Shaojun Wei, Leibo Liu, P.h.D student Zhiheng Yue, M.S. student Te Hu, Hao Li, Yabing Wang and R.D. Limei Tang at the School of Integrated Circuits, Tsinghua University; Prof. Qiang Li, P.h.D student Xin Si at University of Electronic Science and Technology of China; Prof. Meng-Fan Chang at NTHU.

The 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA) was held virtually from Feb. 27 to Mar. 3, 2021. Jianxun Yang, PhD student from Thinker-Lab, gave an oral presentation titled “FuseKNA: Fused Kernel Convolution based Accelerator for Deep Neural Networks”. The paper proposes a novel convolution computation algorithm and architecture to reduce massive redundant operations existed in bit-serial computations of convolutions in CNNs. Jianxun Yang (PhD student) is the first author, and Professor Shouyi Yin is the corresponding author. The paper is also co-authored by Prof. Shaojun Wei, Prof. Leibo Liu, and Zhao Zhang, Zhuangzhi Liu, Jing Zhou (M.S. students).

The 2021 Symposium on VLSI Circuits was held online from June 13th to June 19th. Ruiqi Guo, the Ph.D. student from Thinker-Lab, gave an oral presentation titled “A 6.54-to-26.03 TOPS/W Computing-In-Memory RNN Processor using Input Similarity Optimization and Attention-based Context-breaking with Output Speculation” They proposed a RNN processor with computing-in-memory based architecture. Ruiqi Guo is the first author of this paper, and professor Shouyi Yin is the corresponding author. This paper is also co-authored by Prof. Shaojun Wei, Leibo Liu, M.S. student Hao Li,  and R.D. Limei Tang, Hao Sun at the School of Integrated Circuits, Tsinghua University; Prof. Meng-Fan Chang, M.S. student Zhixiao Zhang, Ruhui Liu at NTHU.

The 2021 Symposium on VLSI Circuits was held online from June 13th to June 19th. Yang Wang, the postdoctoral researcher from Thinker-Lab, gave an oral presentation titled “A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.” The proposed processor can improve the adaptivity of DNN models while reducing the required training energy efficiency. Yang Wang is the first author of this paper, and professor Shouyi Yin is the corresponding author. This paper is also co-authored by Prof. Shaojun Wei, Leibo Liu, Ph.D. student Yubin Qin and M.S. student Dazheng Deng at the School of Integrated Circuits, Tsinghua University.

The 3rd INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS was held online from June 6th to June 9th. Yang Wang, the postdoctoral researcher from Thinker-Lab, gave an oral presentation titled “HPPU: An Energy-Efficient Sparse DNN Training Processor with Hybrid Weight Pruning.” The proposed approach can achieve a high pruning ratio while maintaining the hardware-friendly property for the processor. Yang Wang is the first author of this paper, and professor Shouyi Yin is the corresponding author. This paper is also co-authored by Prof. Shaojun Wei, Leibo Liu, Ph.D. student Yubin Qin at the School of Integrated Circuits, Tsinghua University.

"Efficient Scheduling of Irregular Network Structures on CNN Accelerators" is the winner of 16th ESWEEK Best Paper Award. With the proposed automated compilation framework, the peformance of edge inference devices can be significantly boosted. The first author of this paper is Shixuan Zheng, doctoral candidate in School of Integrated Circuits. The corresponding author is Prof. Shouyi Yin at Tsinghua University.

Ph.D. student Ruiqi Guo from Thinker-Lab,gave an oral presentation titled "A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM macros in 65nm CMOS". At Symposia on VLSI Technology and Circuits,Kyoto,JP, 2019. The authors of the paper include: Ruiqi Guo ,Yonggang Liu ,Shixuan Zheng ,Ssu-Yen Wu ,Peng Ouyang ,Win-San Khwa ,Xi Chen ,Jia-Jing Chen , Xiudong Li , Leibo Liu , Meng-Fan Chang , Shaojun Wei and Shouyi Yin*.

The 55th Design Automation Conference (DAC) was held in San Francisco, CA, USA at the Moscone Center West, from June 24-28, 2018. Xinhan Lin, PhD student from Thinker-Lab, gave an oral presentation titled “LCP: Layer Clusters Paralleling mapping mechanism for accelerating Inception and Residual networks on FPGA” on June 26, 2018. His mapping method can significantly improve the performance of Inception and Residual modules computing on FPGA. Xinhan Lin, (PhD student) is the first author, professor Shouyi Yin is the corresponding author. This paper is also co-authored by Prof. Shaojun Wei, Leibo Liu, Xiangyu Li, Ph.D. student Fengbin Tu at Tsinghua University. 

The 45th International Symposium on Computer Architecture (ISCA) was held in Los Angeles, California, from June 2nd to June 6th. Fengbin Tu, PhD student from Thinker-Lab, gave an oral presentation titled “RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM”on June 4th. His approach to this work can significantly improve the energy efficiency of Artificial Intelligence (AI) Chips. Fengbin Tu (Ph.D. student) is the first author, and Shouyi Yin, Associate Professor at the Institute of Microelectronics, is the corresponding author. The paper is also co-authored by Prof. Shaojun Wei, Prof. Leibo Liu and Weiwei Wu (M.S. student) at the Institute of Microelectronics, Tsinghua University.

Ph.D. student Jianxun Yang,from Thinker-Lab,gave an oral presentation titled“An ultra-high energy-efficient reconfigurable processor for deep neural networks with binary/ternary weights in 28nm CMOS”,at Symposia on VLSI Technology and Circuits,Honolulu,USA, 2018. The authors of the paper include: Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei.

Ph.D. student Shixuan Zheng,from Thinker-Lab,gave an oral presentation titled“A 141 uW, 2.46pJ/Neuron Binarized Convolutional Neural Network based Self-learning Speech Recognition Processor in 28nm CMOS”,at Symposia on VLSI Technology and Circuits,Honolulu,USA, 2018. The authors of the paper include: Shouyi Yin, Peng Ouyang, Shixuan Zheng, Dandan Song, Xiudong Li, Leibo Liu, Shaojun Wei.